mirror of
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376 lines
15 KiB
Scheme
376 lines
15 KiB
Scheme
;;; GNU Guix --- Functional package management for GNU
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;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
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;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org>
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;;; Copyright © 2018, 2019, 2020 Tobias Geerinckx-Rice <me@tobias.gr>
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;;; Copyright © 2019 Amin Bandali <bandali@gnu.org>
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;;;
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;;; This file is part of GNU Guix.
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;;;
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;;; GNU Guix is free software; you can redistribute it and/or modify it
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;;; under the terms of the GNU General Public License as published by
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;;; the Free Software Foundation; either version 3 of the License, or (at
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;;; your option) any later version.
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;;;
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;;; GNU Guix is distributed in the hope that it will be useful, but
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;;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;;; GNU General Public License for more details.
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;;;
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;;; You should have received a copy of the GNU General Public License
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;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
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(define-module (gnu packages fpga)
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#:use-module ((guix licenses) #:prefix license:)
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#:use-module (guix packages)
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#:use-module (guix download)
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#:use-module (guix git-download)
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#:use-module (guix build-system gnu)
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#:use-module (guix build-system cmake)
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#:use-module (gnu packages)
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#:use-module (gnu packages compression)
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#:use-module (gnu packages pkg-config)
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#:use-module (gnu packages tcl)
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#:use-module (gnu packages readline)
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#:use-module (gnu packages python)
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#:use-module (gnu packages bison)
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#:use-module (gnu packages flex)
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#:use-module (gnu packages gtk)
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#:use-module (gnu packages graphviz)
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#:use-module (gnu packages libffi)
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#:use-module (gnu packages linux)
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#:use-module (gnu packages maths)
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#:use-module (gnu packages perl)
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#:use-module (gnu packages ghostscript)
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#:use-module (gnu packages gperf)
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#:use-module (gnu packages gawk)
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#:use-module (gnu packages version-control)
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#:use-module (gnu packages qt)
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#:use-module (gnu packages boost)
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#:use-module (gnu packages algebra)
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#:use-module (gnu packages libftdi))
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(define-public abc
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(let ((commit "5ae4b975c49c")
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(revision "1"))
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(package
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(name "abc")
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(version (git-version "0.0" revision commit))
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(source (origin
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(method url-fetch)
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(uri
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(string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip"))
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(file-name (string-append name "-" version "-checkout.zip"))
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(sha256
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(base32
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"1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
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(build-system gnu-build-system)
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(native-inputs
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`(("unzip" ,unzip)))
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(inputs
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`(("readline" ,readline)))
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(arguments
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`(#:tests? #f ; no check target
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#:phases
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(modify-phases %standard-phases
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(delete 'configure)
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(replace 'install
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(lambda* (#:key outputs #:allow-other-keys)
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(let* ((out (assoc-ref outputs "out"))
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(out-bin (string-append out "/bin")))
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(install-file "abc" out-bin)))))))
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(home-page "https://people.eecs.berkeley.edu/~alanmi/abc/")
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(synopsis "Sequential logic synthesis and formal verification")
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(description "ABC is a program for sequential logic synthesis and
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formal verification.")
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(license
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(license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants")))))
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(define-public iverilog
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(package
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(name "iverilog")
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(version "10.3")
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(source (origin
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(method url-fetch)
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(uri
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(string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/"
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"verilog-" version ".tar.gz"))
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(sha256
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(base32
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"1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6"))))
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(build-system gnu-build-system)
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(native-inputs
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`(("flex" ,flex)
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("bison" ,bison)
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("ghostscript" ,ghostscript))) ; ps2pdf
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(home-page "http://iverilog.icarus.com/")
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(synopsis "FPGA Verilog simulation and synthesis tool")
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(description "Icarus Verilog is a Verilog simulation and synthesis tool.
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It operates as a compiler, compiling source code written in Verilog
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(IEEE-1364) into some target format.
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For batch simulation, the compiler can generate an intermediate form
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called vvp assembly.
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This intermediate form is executed by @command{vvp}.
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For synthesis, the compiler generates netlists in the desired format.")
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;; GPL2 only because of:
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;; - ./driver/iverilog.man.in
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;; - ./iverilog-vpi.man.in
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;; - ./tgt-fpga/iverilog-fpga.man
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;; - ./vvp/vvp.man.in
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;; Otherwise would be GPL2+.
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;; You have to accept both GPL2 and LGPL2.1+.
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(license (list license:gpl2 license:lgpl2.1+))))
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(define-public yosys
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(package
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(name "yosys")
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(version "0.9")
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/cliffordwolf/yosys.git")
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(commit (string-append "yosys-" version))
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(recursive? #t))) ; for the ‘iverilog’ submodule
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(sha256
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(base32
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"0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
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(file-name (git-file-name name version))
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(modules '((guix build utils)))
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(snippet
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'(begin
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(substitute* "Makefile"
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(("ABCREV = .*") "ABCREV = default\n"))
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#t))))
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(build-system gnu-build-system)
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(arguments
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`(#:test-target "test"
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#:make-flags (list "CC=gcc"
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"CXX=g++"
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(string-append "PREFIX=" %output))
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#:phases
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(modify-phases %standard-phases
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(add-before 'configure 'fix-paths
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(lambda _
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(substitute* "./passes/cmds/show.cc"
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(("exec xdot") (string-append "exec " (which "xdot")))
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(("dot -") (string-append (which "dot") " -"))
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(("fuser") (which "fuser")))
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#t))
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(replace 'configure
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(lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
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(apply invoke "make" "config-gcc" make-flags)))
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(add-after 'configure 'prepare-abc
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(lambda* (#:key inputs #:allow-other-keys)
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(let* ((sourceabc (assoc-ref inputs "abc"))
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(sourcebin (string-append sourceabc "/bin"))
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(source (string-append sourcebin "/abc")))
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(mkdir-p "abc")
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(call-with-output-file "abc/Makefile"
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(lambda (port)
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(format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
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(copy-file source "abc/abc")
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(invoke "chmod" "+w" "abc/abc"))))
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(add-before 'check 'fix-iverilog-references
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(lambda* (#:key inputs native-inputs #:allow-other-keys)
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(let* ((xinputs (or native-inputs inputs))
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(xdirname (assoc-ref xinputs "iverilog"))
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(iverilog (string-append xdirname "/bin/iverilog")))
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(substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
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"./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
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"./techlibs/ice40/tests/test_bram.sh"
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"./techlibs/ice40/tests/test_ffs.sh"
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"./techlibs/xilinx/tests/bram1.sh"
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"./techlibs/xilinx/tests/bram2.sh"
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"./tests/bram/run-single.sh"
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"./tests/realmath/run-test.sh"
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"./tests/simple/run-test.sh"
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"./tests/techmap/mem_simple_4x1_runtest.sh"
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"./tests/tools/autotest.sh"
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"./tests/vloghtb/common.sh")
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(("if ! which iverilog") "if ! true")
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(("iverilog ") (string-append iverilog " "))
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(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
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iverilog "\"")))
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#t))))))
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(native-inputs
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`(("pkg-config" ,pkg-config)
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("python" ,python)
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("bison" ,bison)
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("flex" ,flex)
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("gawk" , gawk) ; for the tests and "make" progress pretty-printing
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("tcl" ,tcl) ; tclsh for the tests
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("iverilog" ,iverilog))) ; for the tests
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(inputs
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`(("tcl" ,tcl)
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("readline" ,readline)
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("libffi" ,libffi)
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("graphviz" ,graphviz)
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("psmisc" ,psmisc)
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("xdot" ,xdot)
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("abc" ,abc)))
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(propagated-inputs
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`(("z3" ,z3))) ; should be in path for yosys-smtbmc
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(home-page "http://www.clifford.at/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(license license:isc)))
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(define-public icestorm
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(let ((commit "0ec00d892a91cc68e45479b46161f649caea2933")
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(revision "3"))
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(package
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(name "icestorm")
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(version (git-version "0.0" revision commit))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/cliffordwolf/icestorm.git")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"1qlh99fafb7xga702k64fmc9m700nsddrfgcq4x8qn8fplsb64f1"))))
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(build-system gnu-build-system)
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(arguments
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`(#:tests? #f ; no unit tests that don't need an FPGA exist.
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#:make-flags (list "CC=gcc" "CXX=g++"
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(string-append "PREFIX=" (assoc-ref %outputs "out")))
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#:phases
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(modify-phases %standard-phases
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(add-after 'unpack 'remove-usr-local
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(lambda _
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(substitute* "iceprog/Makefile"
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(("-I/usr/local/include") "")
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(("-L/usr/local/lib") ""))
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#t))
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(add-after 'remove-usr-local 'fix-usr-local
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(lambda* (#:key outputs #:allow-other-keys)
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(substitute* "icebox/icebox_vlog.py"
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(("/usr/local/share") (string-append (assoc-ref outputs "out") "/share")))
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#t))
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(delete 'configure))))
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(inputs
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`(("libftdi" ,libftdi)))
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(native-inputs
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`(("python-3" ,python)
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("pkg-config" ,pkg-config)))
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(home-page "http://www.clifford.at/icestorm/")
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(synopsis "Project IceStorm - Lattice iCE40 FPGAs bitstream tools")
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(description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools.
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Includes the actual FTDI connector.")
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(license license:isc))))
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(define-public nextpnr-ice40
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(let [(commit "c192ba261d77ad7f0a744fb90b01e4a5b63938c4")
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(revision "0")]
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(package
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(name "nextpnr-ice40")
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(version (git-version "0.0.0" revision commit))
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "git://github.com/YosysHQ/nextpnr")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"0g2ar1z89b31qw5vgqj2rrcv9rzncs94184dgcsrz19p866654mf"))))
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(inputs
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`(("qtbase" ,qtbase)
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("boost" ,boost-with-python3)
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("yosys" ,yosys)
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("eigen" ,eigen)
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("python" ,python)
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("icestorm" ,icestorm)))
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(build-system cmake-build-system)
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(arguments
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`(#:configure-flags `("-DARCH=ice40"
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,(string-append "-DICEBOX_ROOT="
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(assoc-ref %build-inputs "icestorm")
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"/share/icebox"))
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#:tests? #f))
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(synopsis "Place-and-Route tool for FPGAs")
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(description "Nextpnr aims to be a vendor neutral, timing driven,
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FOSS FPGA place and route tool.")
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(home-page "https://github.com/YosysHQ/nextpnr")
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(license license:expat))))
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(define-public arachne-pnr
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(let ((commit "840bdfdeb38809f9f6af4d89dd7b22959b176fdd")
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(revision "2"))
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(package
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(name "arachne-pnr")
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(version (string-append "0.0-" revision "-" (string-take commit 9)))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/arachne-pnr.git")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"1dqvjvgvsridybishv4pnigw9gypxh7r7nrqp9z9qq92v7c5rxzl"))))
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(build-system gnu-build-system)
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(arguments
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`(#:test-target "test"
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#:make-flags
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(list (string-append "DESTDIR=" (assoc-ref %outputs "out"))
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(string-append "ICEBOX=" (string-append
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(assoc-ref %build-inputs "icestorm")
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"/share/icebox")))
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#:phases (modify-phases %standard-phases
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(replace 'configure
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(lambda* (#:key outputs inputs #:allow-other-keys)
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(substitute* '("./tests/fsm/generate.py"
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"./tests/combinatorial/generate.py")
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(("#!/usr/bin/python") "#!/usr/bin/python2"))
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#t)))))
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(inputs
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`(("icestorm" ,icestorm)))
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(native-inputs
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`(("git" ,git) ; for determining its own version string
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("yosys" ,yosys) ; for tests
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("perl" ,perl) ; for shasum
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("python-2" ,python-2))) ; for tests
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(home-page "https://github.com/YosysHQ/arachne-pnr")
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(synopsis "Place-and-Route tool for FPGAs")
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(description "Arachne-PNR is a Place-and-Route Tool For FPGAs.")
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(license license:gpl2))))
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(define-public gtkwave
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(package
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(name "gtkwave")
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(version "3.3.104")
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(source
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(origin
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(method url-fetch)
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(uri (list (string-append "mirror://sourceforge/gtkwave/"
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"gtkwave-" version "/"
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"gtkwave-" version ".tar.gz")
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(string-append "http://gtkwave.sourceforge.net/"
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"gtkwave-" version ".tar.gz")))
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(sha256
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(base32 "0kw9a33gx60kn069yhx5pyk39x1z3pwaj8l1qqwq943v62lx23fj"))))
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(build-system gnu-build-system)
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(native-inputs
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`(("gperf" ,gperf)
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("pkg-config" ,pkg-config)))
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(inputs
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`(("tcl" ,tcl)
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("tk" ,tk)
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("gtk+-2" ,gtk+-2)))
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(arguments
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`(#:configure-flags
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(list (string-append "--with-tcl="
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(assoc-ref %build-inputs "tcl")
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"/lib")
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(string-append "--with-tk="
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(assoc-ref %build-inputs "tk")
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"/lib"))))
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(synopsis "Waveform viewer for FPGA simulator trace files")
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(description "This package is a waveform viewer for FPGA
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simulator trace files (@dfn{FST}).")
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(home-page "http://gtkwave.sourceforge.net/")
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;; Exception against free government use in tcl_np.c and tcl_np.h.
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(license (list license:gpl2+ license:expat license:tcl/tk))))
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