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* gnu/packages/patches/qemu-CVE-2015-4037.patch, gnu/packages/patches/qemu-CVE-2015-4103.patch, gnu/packages/patches/qemu-CVE-2015-4104.patch, gnu/packages/patches/qemu-CVE-2015-4105.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt1.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt2.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt3.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt4.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt5.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt6.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt7.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt8.patch: New files. * gnu-system.am (dist_patch_DATA): Add them. * gnu/packages/qemu.scm (qemu-headless)[source]: Add patches.
72 lines
2.5 KiB
Diff
72 lines
2.5 KiB
Diff
From d1d35cf4ffb6a60a356193397919e83306d0bb74 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 2 Jun 2015 15:07:01 +0000
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Subject: [PATCH] xen/MSI: don't open-code pass-through of enable bit
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modifications
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Without this the actual XSA-131 fix would cause the enable bit to not
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get set anymore (due to the write back getting suppressed there based
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on the OR of emu_mask, ro_mask, and res_mask).
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Note that the fiddling with the enable bit shouldn't really be done by
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qemu, but making this work right (via libxc and the hypervisor) will
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require more extensive changes, which can be postponed until after the
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security issue got addressed.
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This is a preparatory patch for XSA-131.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
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---
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hw/xen/xen_pt_config_init.c | 10 ++--------
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1 file changed, 2 insertions(+), 8 deletions(-)
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diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
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index 68b8f22..436d0fd 100644
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--- a/hw/xen/xen_pt_config_init.c
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+++ b/hw/xen/xen_pt_config_init.c
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@@ -1053,7 +1053,6 @@ static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
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XenPTMSI *msi = s->msi;
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uint16_t writable_mask = 0;
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uint16_t throughable_mask = 0;
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- uint16_t raw_val;
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/* Currently no support for multi-vector */
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if (*val & PCI_MSI_FLAGS_QSIZE) {
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@@ -1066,12 +1065,11 @@ static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
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msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
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/* create value for writing to I/O device register */
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- raw_val = *val;
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throughable_mask = ~reg->emu_mask & valid_mask;
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*val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
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/* update MSI */
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- if (raw_val & PCI_MSI_FLAGS_ENABLE) {
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+ if (*val & PCI_MSI_FLAGS_ENABLE) {
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/* setup MSI pirq for the first time */
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if (!msi->initialized) {
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/* Init physical one */
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@@ -1099,10 +1097,6 @@ static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
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xen_pt_msi_disable(s);
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}
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- /* pass through MSI_ENABLE bit */
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- *val &= ~PCI_MSI_FLAGS_ENABLE;
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- *val |= raw_val & PCI_MSI_FLAGS_ENABLE;
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-
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return 0;
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}
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@@ -1301,7 +1295,7 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = {
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.size = 2,
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.init_val = 0x0000,
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.ro_mask = 0xFF8E,
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- .emu_mask = 0x017F,
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+ .emu_mask = 0x017E,
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.init = xen_pt_msgctrl_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_msgctrl_reg_write,
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--
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2.2.1
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