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* gnu/packages/patches/qemu-CVE-2015-4037.patch, gnu/packages/patches/qemu-CVE-2015-4103.patch, gnu/packages/patches/qemu-CVE-2015-4104.patch, gnu/packages/patches/qemu-CVE-2015-4105.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt1.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt2.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt3.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt4.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt5.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt6.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt7.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt8.patch: New files. * gnu-system.am (dist_patch_DATA): Add them. * gnu/packages/qemu.scm (qemu-headless)[source]: Add patches.
72 lines
2.2 KiB
Diff
72 lines
2.2 KiB
Diff
From a88a3f887181605f4487a22bdfb7d87ffafde5d9 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 2 Jun 2015 15:07:01 +0000
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Subject: [PATCH] xen/pt: add a few PCI config space field descriptions
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Since the next patch will turn all not explicitly described fields
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read-only by default, those fields that have guest writable bits need
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to be given explicit descriptors.
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This is a preparatory patch for XSA-131.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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---
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hw/xen/xen_pt_config_init.c | 28 ++++++++++++++++++++++++++++
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1 file changed, 28 insertions(+)
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diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
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index efd8bac..19f926b 100644
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--- a/hw/xen/xen_pt_config_init.c
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+++ b/hw/xen/xen_pt_config_init.c
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@@ -754,6 +754,15 @@ static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
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.u.b.write = xen_pt_byte_reg_write,
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},
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{
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+ .offset = PCI_VPD_ADDR,
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+ .size = 2,
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+ .ro_mask = 0x0003,
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+ .emu_mask = 0x0003,
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+ .init = xen_pt_common_reg_init,
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+ .u.w.read = xen_pt_word_reg_read,
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+ .u.w.write = xen_pt_word_reg_write,
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+ },
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+ {
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.size = 0,
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},
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};
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@@ -889,6 +898,16 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_word_reg_write,
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},
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+ /* Device Status reg */
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+ {
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+ .offset = PCI_EXP_DEVSTA,
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+ .size = 2,
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+ .res_mask = 0xFFC0,
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+ .ro_mask = 0x0030,
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+ .init = xen_pt_common_reg_init,
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+ .u.w.read = xen_pt_word_reg_read,
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+ .u.w.write = xen_pt_word_reg_write,
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+ },
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/* Link Control reg */
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{
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.offset = PCI_EXP_LNKCTL,
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@@ -900,6 +919,15 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_word_reg_write,
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},
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+ /* Link Status reg */
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+ {
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+ .offset = PCI_EXP_LNKSTA,
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+ .size = 2,
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+ .ro_mask = 0x3FFF,
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+ .init = xen_pt_common_reg_init,
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+ .u.w.read = xen_pt_word_reg_read,
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+ .u.w.write = xen_pt_word_reg_write,
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+ },
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/* Device Control 2 reg */
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{
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.offset = 0x28,
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--
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2.2.1
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